ANI 1 Input Interface Figure 008
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 ANI 2 Input Interface Figure 009
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 Encoder Figure 010
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 Using the boards CPU (in COM) or MPU (in MON), the encoder forms a loop which, after successive corrections on VD gives:
 VD = VX / VR
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 (c)
 ANI 3 input - Position of the servovalve selector valve (MAN board) Interface for one channel (Ref. Fig. 011) The interface performs: Vs = Vs1 - Vs2 which is then demodulated by a square AC reference. A low-pass filter of the 2nd order eliminates the signal harmonics. Voltages Vx are then multiplexed to be digital-encoded.

 (d)
 ANI 4 input - Accelerometers (CAN and MAN boards) Interface for one input* (Ref. Fig. 012) The interface performs the differential acquisition of the low-impedance DC signal. A low-pass filter of the 2nd order suppresses interference. Voltages Vx are then multiplexed and encoded.

 (e)
 ANO output - servovalve current (CAN board) The digital value which represents the servovalve current is loaded into the 12-bit DAC of the encoding interface which converts it into an analog voltage VA. This voltage multiplexed according to the channel, is then memorized in a capacitor which serves, with the next stage, as a sampler/holder. The output from this stage (VAF) controls the power amplifier, wired as a voltage follower in order to generate the servovalve control current. (Ref. Fig. 013)

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 ANI 3 Input Interface Figure 011
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 ANI 4 Input Interface Figure 012
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 Analog Output Figure 013
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 (f)
 ANI 5 inputs - Wraparound of servovalve current (CAN board) The resistor which programs the servovalve current is divided into two parts. (Ref. Fig. 014) The intermediate points are internally multiplexed and encoded. This enables the COM unit to check that the servovalve current is equal to the current that it has controlled.

 (g)
 ANI 7 inputs - Position of solenoid valve selector valves (MAN boards) Interface for one channel* (Ref. Fig. 015) The interface performs the differential acquisition of the input which is demodulated, filtered then multiplexed and encoded.

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 ANI 5 Input Interface Figure 014
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 ANI 7 Input Interface Figure 015
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 (3)
 CDG - MDG boards These boards manage the digital input and output busses to ARINC 429 standard. These boards are identical in COM and in MON. The first function of this board is to perform the reception, acquisition, recognition and storage of the received messages. The second function of this board is to perform (upon CPU request) the generation, checking, shaping and transmission of messages on the outputs. All data exchanged between the CPU and CDG transit via a buffer memory located on the CDG boards. This memory enables the two microprocessors to perform mutual monitoring. This board includes:

 -a 16-bit microprocessor of the 68000 family,
 -
the circuits required for microprocessor starting,

 -
the clock circuits,

 -
a program memory (EPROM : 16 Kwords of 16 bits),

 -
a data memory (SRAM : 2 Kwords of 16 bits),

 -three timers for program synchronization,
 -the interrrupt management circuits.

 (4)
 CPS-MPS boards These cards (CPS in COM and MPS in MON) are identical and perform the functions below (Ref. Fig. 006, 007)

 -generation of voltage sources required for unit operation:
 +5V, ± 15V.

 -support of discrete outputs and switching relays.
 The power supply section includes:

 -
the protection and filtering of interference on the 28VDC.

 -
the conversion of 28V from electrical network into +5V and ±15V.

 -
the monitoring: . of the network voltage : as soon as it is lower than 17V, a P OFF signal is generated. . of the primary current : a limitation is performed. . of the +5V at the secondary : as soon as this voltage is higher than 4.75V, a validity signal (P WON) is generated.
　
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