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時間:2011-03-22 06:40來源:藍天飛行翻譯 作者:admin
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 ELAC Architecture Figure 005
 1EFF : 1 1R 1CES  ALL  1 11 1 27-93-00 Page 13 Feb 01/00

 

 The other functions are:
 -acquisition of analog inputs and generation of analog outputs (CAN and MAN boards)
 -generation of discrete outputs and control of switching relays (MSP
 and CPS boards). The slave processor (CSP and MSP boards) computes the laws and the logic. It communicates with the main processor through a buffer memory. The data transmission between boards is made through the bus located at the bottom part of the casing. This bus is under the exclusive control of the main processor. The main processor directly controls the relay outputs. However, the specialized processor of the digital acquisition board can de-activate these relays or discrete outputs through a separate control. The power supplies generated independently in each unit are distributed at the bottom of the casing to the other boards of the unit. The control and monitoring channels exchange data through ARINC 429 and discrete links outside the casing.
 B. Description of Boards
 (1) CPU - MPU boards These boards are identical and integrate the unit main processor. They also include the interfaces with the discrete inputs. Several components are shown (Ref. Fig. 006, 007)
 -
the 16-bit microprocessor of the 68000 family,


 -
the clock and bus management circuitry,


 -
the circuits required for microprocessor start and restart,


 -
the read-write memory of the SRAM type (4 Kbytes),


 -
the interrupt management circuits for the microprocessor,


 -
the interface with the bus,


 -
the real-time clock,


 -
the watchdogs,


 -
the non-volatile memory (NVRAM).
 The purpose of this memory is to save the data related to the
 failures detected during operation if a power supply cutoff occurs.
 This memory can be used in maintenance (BITE) (for shop maintenance
 only).
 The saving or recall of data is made upon software command.
 Discrete inputs
 The discrete input interfaces receive:

 

 -40 GROUND-OPEN inputs

 -
8 28VDC-OPEN inputs


 -
8 reconfigurable inputs

 

 1EFF : ALL 1 27-93-00Page 14 1 1 Feb 01/00R 1 1 1CES 1


 COM Unit Architecture
 Figure 006

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1


 MON Unit Architecture
 Figure 007

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1


 The interfaces ensure the translation of the input levels into
 TTL-compatible levels (0-5V).
 These 56 inputs are then multiplexed so as to make four 16-bit words
 that can be accessed by the microprocessor software.

 (2) CAN-MAN boards These boards manage the analog inputs from the various aircraft transducers. In particular, they ensure the analog/digital conversion of these data. The MAN (in MON) and CAN (in COM) boards are of identical constitution for certain inputs. The main differences are:
 -
The MAN board processe additional inputs for the monitoring of servocontrols (Ref. Fig. 006)

 -
The CAN board performs the digital/analog conversion of the
 servovalve control outputs
 (Ref. Fig. 007)
 These boards ensure the functions below:

 

 -processing of inputs
 -multiplexing of DC voltages and analog/digital conversion
 -generation of DC and AC references for the board
 -DC and AC power supply of the transducers (+10VDC and 7V, 1953 Hz)
 -interface with the microprocessor bus and check of the board functions
 -protections against the application of a spurious overvoltage (lightning strike etc.).
 (a)
 ANI 1 inputs - side stick transducers (CAN and MAN boards) Schematic of interface for one channel (Ref. Fig. 008) The two input amplifiers are wired as followers. The SURV ouptut permits to detect the cutoff of the potentiometer supply points. The cutoff at level of the slider or of the mid point puts Vx out of range. A low-pass filter of the 2nd order suppresses interference. Voltage Vx is then multiplexed and digital-encoded.

 (b)
 ANI 2 input - Servocontrol position feedbacks (CAN and MAN boards). Schematic of interface for one channel* (Ref. Fig. 009) With V1 = U11 - U12 and V2 = U21 - U22, the interface performs: VR = V1 - V2 and VX = V1 + V2. Voltages VR and Vx are then multiplexed to drive the encoder (Ref. Fig. 010)


 1EFF : ALL 1 27-93-00Page 19 1 1 Feb 01/00R 1 1 1CES 1
 
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