C. Particular Points
 -In the event of multiples failures affecting certain LRUs of a same type, the FCDC will, in certain cases, give only one message;
 (e.g left and right throttles failed: one message only However, if accelerometers 1 and 2 failed: two messages).
 -
The surface position is given by the computer which controls the surface except for the ailerons, the position is given by the computer in standby

 -
The indication SPOILER OUT is given for a deflection higher than 2.5 deg.

 -Some periodic tests are performed by the FCDC
 -Test generated by the FCDC: Damping test

R  7. Test____ 
R  A. General 
R  The FCDC is equipped with integrated test functions which provide a high 
R  degree of failure detection, identification and isolation. Confirmed 
R  failures are stored in a particular zone of non-volatile memory for later 
R  display in a maintenance mode.

 B. Self Test
 (1)
 Basic Test Upon power-on, the FCDC is initialized and starts its internal self test-functions (BITE). These are : (Ref. Fig. 015)

 -partial BITE if power supply interrupt is less than 3 seconds A/C on ground or if power supply interrupt is more than 3 seconds A/C in flight
 -complete BITE if power supply interrupt is more than 3 seconds A/C on ground.

 (2)
 Memory A bytewise checksum method is employed to check the correct operation of each half of the EPROM-type memories. To check if all local RAM memory cells can be set and cleared, two bit patterns, Hex "5555" and Hex "AAAA", are written to each RAM memory location and read back.

 (3)
 Timers The real time counter is tested initially for correct operation by measuring the elapsed time between two successive interrupts. The two other timers (bus time out supervisor and watchdog timer) are then checked to ensure that they expire and generate a failure signal if they are not reset in time.

 (4)
 ARINC 429 Channels The two inputs and the output of each ARINC 429 chip are tested using wraparound techniques. On a first level (digital signals), both receivers are provided with the actual information from the transmitter of the chip. The test result is achieved from the comparison of the transmitted word with the received word. On a second level (analog signals), a comparison test is performed using the permanent wraparound connection from the driver output to an extra input channel. After having checked the correct operation of each channel, faulty messages are simulated to test the failure recognition capability of the receiver channels.

 (5)
 Discrete Inputs/Outputs The discrete input interfaces are tested using a dedicated test line which is first connected to VCC and then to GND. If the outputs correspond to the polarity of the test line, the interface has passed the test. The discrete outputs (relays) have two contacts. One of these contacts is used for test purposes as follows:

 FCDC-BITE Access
 Figure 015
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 The position of the relay contacts (open, closed) is read and then compared with the actual test pattern.
 (6)
 Analog Inputs One channel of the analog input interface is permanently connected to a fixed voltage derived from the A/D converter. The corresponding digital output value is read and compared with a permitted tolerance band.

 (7)
 Power Supply The discrete signals of the monitored secondary output voltages of plus or minus 15V are read and checked for validity.

 C. System Test The correct operation of the EFCS is checked through the exchange of information among the ELAC, SEC and FCDC computers. These system tests are initialized either automatically or manually.
 D. In-Flight Monitoring Self testing is performed periodically (scheduled in normal mode).
 E. Menu Mode The menu mode is initiated via commands from the CFDIU. A menu-driven control technique is applied for communication between the FCDC and the CFDIU. The FCDC transmits on demand the contents of the non-volatile memory either in plain English or in hexadecimal format. In addition to the display of failure information, all types and levels of tests can be initiated using predefined commands.

R **ON A/C 001-049, 051-060, 101-101,
 F. Power-up Tests Initialization and Cockpit Repercussions
 (1)
 Conditions of power-up tests initialization

 -Computer de-energization time: > 3 s
 -A/C configuration: A/C on ground and engines stopped
　
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