曝光臺 注意防騙 網曝天貓店富美金盛家居專營店坑蒙拐騙欺詐消費者

 1EFF : 106-149, 303-399, 1 31-63-00Page 22 1 1 Config-3 Aug 01/05 1 1 1CES 1 The bus arbiter can receive four bus-request (BR*) signals simultaneously for the use of the COMMON BUS - three from the three I/O interface boards and one from the three DPU boards, which are daisy-chained. Based on the priority rules, the bus arbiter then grants request to that board with the highest priority-level. This is done by activating the specific bus-grant signal (BGIN*). The bus arbiter can transmit four bus grant signals - three to the three I/O interface boards and one to the three daisy-chained DPU boards. Once a bus-request is granted to a board, it asserts the signal BUSY* which informs the bus arbiter that the COMMON BUS is being used. The bus arbiter can treat 6 bus-requests (BR*) with priority and fairness protocol. Fairness: If 3 or more bus requests occur at the same time, all requests will be granted in priority sequence without interruption. The maximum waiting time of a requesting device is the duration of 5 common bus cycles incl. arbitration.

 (b) I/O interface 1, 2 and 3 boards (Ref. Fig. 008) Each of the three interface boards consists of three independent I/O (input/output) interfaces:
 -
the discrete I/O interfaces

 -
the ARINC I/O interfaces

 -
the serial interfaces. The complete management of these interfaces is carried out by the processor logic on each board. The main task of the processor logic is to handle all data passing through these interfaces, relabelling it when necessary and storing it in the COMMON RAM (on the DPU1 (PFD) board). It also fetches data from the COMMON RAM and guides it to external peripherals via these interfaces.

 1EFF : 106-149, 303-399, 1 31-63-00Page 23 1 1 Config-3 Aug 01/05 1 1 1CES 1

 The general function of all three I/O interface boards is
 identical ; each board operating independently due to its own
 processor logic.
 Each I/O interface board consists of five main logic groups:

 -processor logic

 -discrete I/O interface logic

 -ARINC I/O interface logic

 -serial interface logic

 -bus logic.
 There are two logic bus lines on each board : the CPU-bus-lines
 and the I/O-bus-lines. The CPU-DATA-BUS (16-bit, bidirectional,
 three-state) and the CPU-ADDRESS-BUS (20-bit, unidirectional,
 three-state) provide communication with the CPU in the processor
 logic, whereas the I/O-DATA-BUS (16-bit, bidirectional,
 three-state) provides communication with the discrete and ARINC
 I/O interface logic.

 1_ Processor logic
 The following functional groups are discussed under this
 heading:
 - Central Processing Unit (CPU)
 - local data RAM, program PROM and relabelling EPROM
 - address decoder and DTACK generator
 - interrupt logic
 - watchdog timer and reset logic
 - clock generator.

 1EFF : 106-149, 303-399, 1 31-63-00Page 24 1 1 Config-3 Aug 01/05 1 1 1CES 1

 I/O Interface Board - Block Diagram
 Figure 008

 1EFF : 106-149, 303-399, 1 31-63-00Page 25/26 1 1 Config-3 Aug 01/05 1 1 1CES
1

 a
_
 b
_
Central Processing Unit (CPU)
 The CPU is a 16-bit microprocessor from the MC68020 family.
 It is always in one of the following three processing
 states:

 -normal processing state, which is associated with intruction execution. In this state, the CPU fetches instructions/operands from its program PROM or the COMMON RAM, processes them and stores the final result back in the COMMON RAM. (The COMMON RAM is located on the DPU1 (PFD) board)
 -execution processing state, which is associated with interrupts, trap instructions and other exceptional conditions. In this case, a vector number, which is fetched from the program PROM, is fed to the CPU via the CPU-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the program PROM. The CPU executes this instruction in order to carry out the necessary is executed by the CPU in order to carry out the necessary
 -halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
Local data RAM, program PROM and relabelling EPROM When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 2Kx16-bit local data RAM. The program PROM has a total storage capacity of 8Kx16-bit words. It contains the instructions carried out by the CPU during its normal processing state as well as the exception vectors required during the exception processing state - in short, the complete operational software required by this board is stored in the program PROM. The relebelling EPROM has a total storage capacity of 32Kx16-bit words. The relabelled addresses for the COMMON RAM (for the data received through the ARINC I/O interface logic) as well as the test library (for the self tests) and a monitoring program for this board (for maintenance operations) are stored in the relabelling EPROM. All three memories are addressed by the CPU-ADDRESS-BUS and data transfer takes place through the CPU-DATA-BUS. The address decoder provides the enable-signals and the CPU the read/write signals.
　
中國航空網 m.k6050.com
航空翻譯 www.aviation.cn
本文鏈接地址：A320飛機維護手冊 AMM 指示/記錄系統 7(145)