WXR Board - Block Diagram
 Figure 010

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 Conversion of Manchester Bits to TTL-Levels
 Figure 011

R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 41 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 During a test operation of the WXR board, the DPU2 (ND) board activates the signal TEST ON in word register 6, which switches the MUX to select a simulated beam from the test pattern generation logic and sends it to the manchester decoder. The manchester decoder is responsible for determining the beginning and the end of each serial input word received from the ARINC 708 interface and converting the input bits to NRZ (non-return to zero) bits. It consists of a shift register, a latch and a bit detection PROM. The serial data input is continuously sampled at 8 MHz, i.e., each input bit is sampled 8 times, out of which the first and last samples are disregarded. The sample result is latched and forms the address to the bit detection PROM. When the PROM receives the 3 sequential addresses denoted by START SYNC, it is conditioned to decode the subsequent data bits into NRZ code. (Ref. Fig. 012) Each bit in the four control words as well as in the following BIN information is converted from a manchester-bit to a NRZ-bit. When the bit detection PROM receives the 3 sequential addresses denoted by END SYNC, this indicates that a complete valid beam information has been decoded by the manchester decoder. (Ref. Fig. 013) It will be noted that, after the START SYNC has been detected, the LOOP address is 011. Under this condition all following data bits are converted to NRZ. A change-over from LOW to HIGH in the input data bit corresponds to a LOW NRZ-bit, whereas a change-over from HIGH to LOW in the input data bit corresponds to a HIGH NRZ bit. (Ref. Fig. 014)

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 Manchester Decoder
 Figure 012

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 Conversion of Manchester Bits to NRZ Bits
 Figure 013

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 Examples of Valid and Invalid NRZ Bits
 Figure 014

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Beam shift register and file register After the signal START SYNC has been detected in the input word, the manchester decoder outputs the first 16 NRZ bits of the first control word. These 16 NRZ bits are shifted serially into the beam shift register, under the control of the beam control logic. In order to load these 16-bits into the file register, the beam control logic provides the write-enable signal, whereas the control word counter determines the location of the bits in the file register. In this way all four control words from an input word are eventually stored in the file register. The beam control logic now generates an interrupt, which is transmitted to the DPU2 (ND) board. The interrupt-routine enables the DPU2 (ND) board to fetch the four control words via the bus couplers (slave) and process them. The scan angle of the beam, contained in control word 4, is added to the drift angle on the DPU2 (ND) board and the result - the computed angle - is fed back to the WXR board (COMP. ANGLE at word register 5).
Beam buffer After the four control words have been loaded into the file register, the first BIN (3 bits) in the input word is shifted serially into the beam shift register, under the control of the beam control logic. In order to load the BIN in the beam buffer, the beam control logic provides the write-enable signal and the BIN counter determines the location of the BIN in the beam buffer. The beam buffer is a RAM with a total storage capacity if 1K x 4-bit (only 1K x 3-bit used). In this way, all 512 BINs are eventually transferred to the beam buffer and at any given time, the beam buffer contains the complete color information (512 BINs) of one beam). When the signal END SYNC at the end of the input word is recognized, the beam control logic initiates a read-operation of the beam buffer. During this operation, a BIN (3 bits) is read out and presented to the main memory via four hex line drivers. The three bits in each BIN read out of the beam buffer are fanned out by the hex line drivers so that the main memory, which consists of four modules, receives a total of twelve data-bits ; each module receiving three bits (one BIN). This ensures that all four modules in the main memory are presented with identical BIN information.
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