5. TABLE 5
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A. The DISCRETE I/P STATUS page diplay for the CSU Track Switch Bank A and B R comparison checks.
------------------------------------------------------------------------------SFCC=(1) or (2) ZZZZ DISCRETE I/P STATUS
------------------------------------------------------------------------------CSU TRACK 12345 SWITCH BANK A : ..... SWITCH BANK B : ..... DISCRETE I/P 1 : %%%%%%%% DISCRETE I/P 2 : %%%%%%%% DISCRETE I/P 3 : %%%%%%%% DISCRETE I/P 4 : %%%%%%%% XXXX XXXXX XXXXXXXX XXXX YYY YYYY YYYYY YYYY AOG : * A/C:????? SGOI : . <RETURN> <PRINT>
Explanation:
Where the * = SFCC 1 or 2 (dependent on the selection)
Where the ZZZZ is SLAT or FLAP
Where the XX------XX is = FLAP RELIEF ENABLED.
or = FLAP RELIEF DISABLED. or = FLAP RELIEF CODING FAIL.
Where the YY------YY is = MAX FLAP 35 DEG (CMF).
or = MAX FLAP 40 DEG (IAE).
or = MAX FLAP CODING FAIL.
Where the . is function set (1) or function reset (0).
Where the % is a logic 1 or a logic 0 as given by the input circuit.
Where the ???? is = A320, A321 or FAIL depending on the Aircraft Type pin
program in that channel.
Where AOG means aircraft on ground.
Where SGOI means system ground inhibit.
The CSU is monitored by both lanes of the associated SFCC.
Each lane receives 2 sets of the 5 switch tracks.
Each set has 5 detent patterns, two (2) adjacent switch tracks connected
to return and four (4) OUT-OF- DETENT patterns (one of each track 2, 3,
4, and 5), connected to ground.
B. The Discrete Input Word 1
(1) The Discrete Input Word 1 has the discrete inputs that follow.
R MSB LSB ------------------------------------------------------------------------------A321 ∞ Bank 2 ∞ Bank 2 ∞ Bank 2 ∞ Bank 1 ∞ Bank 1 ∞ Bank 1 ∞ Bank 1 A/C Type∞ CSU ∞ CSU ∞ CSU ∞ CSU ∞ CSU ∞ CSU ∞ CSU Coding 1∞ Switch 4∞ Switch 5∞ Switch 2∞ Switch 4∞ Switch 3∞ Switch 2∞ Switch 1 ------------------------------------------------------------------------------
「一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一1 EFF : ALL ∞∞27-81-00∞∞∞∞∞∞∞∞∞∞Page 310
May 01/05 CES
R (2) The table that follows gives a description of each discrete input.
------------------------------------------------------------------------------Bit ∞ Name ∞ Description ------------------------------------------------------------------------------
0 ∞ BANK 1 CSU SWITCH 1 ∞ The first input from the CSU switch bank 1. ------------------------------------------------------------------------------1 ∞ BANK 1 CSU SWITCH 2 ∞ The second input from the CSU switch bank 1. ------------------------------------------------------------------------------2 ∞ BANK 1 CSU SWITCH 3 ∞ The third input from the CSU switch bank 1. ------------------------------------------------------------------------------3 ∞ BANK 1 CSU SWITCH 4 ∞ The fourth input from the CSU switch bank 1. ------------------------------------------------------------------------------4 ∞ BANK 2 CSU SWITCH 2 ∞ The second input from the CSU switch bank 2. ------------------------------------------------------------------------------5 ∞ BANK 2 CSU SWITCH 5 ∞ The fifth input from the CSU switch bank 2. ------------------------------------------------------------------------------6 ∞ BANK 2 CSU SWITCH 4 ∞ The fourth input from the CSU switch bank 2. ------------------------------------------------------------------------------
7 ∞ A321 A/C TYPE CODING 1 ∞ A/C Type Coding 1/2 shows the aircraft type the ∞ ∞ SFCC is installed on. ∞ ∞ A/C Type Coding 1/2 reset = A321 ∞ ∞ A/C Type Coding 1/2 reset = A320
------------------------------------------------------------------------------
C. The Discrete Input Word 2
(1) The Discrete Input Word 2 has the discrete inputs that follow.
R MSB LSB ------------------------------------------------------------------------------Aircraft∞ Spare ∞ Spare ∞ 28V ∞ Spare ∞ Spare ∞ Bank 1 ∞ Spare on ∞ ∞ ∞ Power ∞ ∞ ∞ CSU ∞ Ground ∞ ∞ ∞ Supply ∞ ∞ ∞ Switch 5∞ ------------------------------------------------------------------------------
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