(g)  
The CPU acquires the input data from the analog and discrete input multiplexers and from the DITS data RAM. The CPU formats the data in 12 bit words that are output in a serial data stream. The output data is bussed to a harvard bi-phase transmitter for output to the DFDR.

 (h)  
The DFDAMU BITE continuously performs internal circuit checks as soon a power is applied. A BITE detected fault is output in a status word to the DFDR and stored in a non-volatile memory for access by shop test equipment. The stored fault data provides a history of intermittent faults as well as identifying current faults. Current faults are indicated by the fault indicator on the DFDAMU's front panel. Current faults are also output to the flight recorder control panel to turn the OFF light on and to the EICAS for message generation.

 (i)  
The DFDAMU monitors all input interface circuits, the CPU instruction set, and all memories for faults so that they may be checked out with shop equipment. The output interface circuits and program timing are also monitored. When a fault is detected, a ground signal is provided to the OFF light on the flight recorder control panel and to the FDAU FAULT light. The DFDR maintenance flag signal is also monitored. When a fault is detected, a ground signal is sent to turn on the DFDR FAULT light.

 (4)  DFDR Functions
 (a)  The DFDR receives 115V ac power from the FLIGHT RECORDER AC circuit breaker through either the manual or automatic switching network. The DFDR contains a regulated power supply that generates the necessary operating voltages.
  GUN 051 ú

 31-31-00
 ú CONFIG ú 01 Page 12 ú Dec 20/93

A

(b)

(c)

(d)

(e)

(f)

(g)

757
MAINTENANCE MANUAL

The DFDR receives flight data from the DFDAMU in a 768 bit per second harvard bi-phase format. The data is converted to NRZ format and one second data blocks are alternately stored in two 768 bit blocks of RAM. Data from one block of RAM is converted back to harvard bi-phase format, written on the tape and verified for proper recording. At the same time, the other block of RAM is storing information.The data is sequentially recorded on either tape tracks to achieve a 25 hour history of airplane operation. Two four track erase heads and two four track read/write heads are used for recording and playback. The proper read/write and erase channels are selected under CPU control based upon the track being recorded and/or operational mode. In the recording mode, the CPU monitors EOT and BOT sensors to initiate track changes at the completion of recording on each track. When the EOT/BOT sensor is detected, the direction of tape travel is changed and the next track is selected for recording. Data that identifies the track being recorded is stored in NVM so that in the event of power interruption, recording can continue on the same track after power is restored.The tape transport is driven by a CPU controlled stepper motor. When operating in the recording mode, the tape is sequentially step driven two increments forward and one increment backward. During the first forward increment, the previously recorded data block is read and verifed. During the second forward increment, the 768 bit data is written on the tape. The tape is next driven backward one increment in preparation for the next cycle.The playback data is sent to the DFDR front panel connector and to the DFDAMU for output to a flight deck test connector. This enables the transfer of the recorded data to a portable copy recorder for ground processing. All eight channels are transferred simultaneously.A primary function of the BITE is to monitor the recording verification that is accomplished during each step. The BITE also monitors tape motion, EOT and BOT sensors, track select, presence of input data, and CPU lock-up. The occurrence of any BITE failure, except for loss of input data, causes the BITE LED on the DFDR's front panel to be lit. A fault signal is also sent to the DFDAMU, flight recorder control panel and to EICAS.When a failure is detected, the output of the fault gate is a logic 1. This sends a maintenance flag discrete signal to the BITE LED on the front panel and to the DFDAMU.
　
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