GUN 001-050, 052-999 ú 31-31-00
ú CONFIG ú 01 Page 12 ú Sep 28/01
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MAINTENANCE MANUAL
Each analog input signal is fed into an isolation network that adjusts the input level. A CPU controlled multiplexer selects one channel at a time for signal processing when it is required for output to the DFDR. The selected input signal then passes through a CPU controlled conditioner that demodulates and scales the signal prior to A/D conversion. The A/D network converts the signal into a 12 bit binary word for further processing by the CPU. Calibration of the analog interface is accomplished automatically by processing a known simulated input signal and revising the signal conditioner gain and offset constants as necessary.Each discrete input enters the DFDAU through a buffer network. When this signal is required for output to the DFDR, it is selected by the CPU controlled multiplexer. The selected input signal then passes through a comparator that threshold compares the signal against a logical 1 and logical 0 criteria. The signal is next converted to CPU compatible levels for further processing.Each digital information transfer system (DITS) input signal enters by a pair of differential comparators that encode the data in a format suitable for processing. The channels are then selected by a multiplexer which is controlled by the DITS channel sequencer.The digital information transfer system (DITS) input signals are coded in ARINC 429 digital data format and are received either at low or high speed. Four of the DITS input channels have the capability to accept either high or low speed ARINC 429 data while the rest of the channels accept only low speed data. Each DITS input signal enters by a pair of differential comparators that encode the data in a format suitable for processing. The channels are then selected by a multiplexer which is controlled by a DITS channel sequencer. The label is read from the incoming data word to identify whether or not the data is stored in the DITS data RAM in a specific location based on input port and label. The CPU then samples the appropriate location in the DITS data RAM to obtain parameter data for output.The CPU acquires the input data from the analog and discrete input multiplexers and from the DITS data RAM. The CPU formats the data in 12 bit words that are output in a serial data stream. The output data is bussed to a harvard bi-phase transmitter for output to the DFDR.The DFDAU BITE continuously performs internal circuit checks as soon a power is applied. A BITE detected fault is output in a status word to the DFDR and stored in a non-volatile memory for access by shop test equipment. The stored fault data provides a history of intermittent faults as well as identifying current faults. Current faults are indicated by the fault indicator on the DFDAU's front panel. Current faults are also output to the FRCP (or FDEP) to turn on the applicable fault light and to the EICAS for message generation. 中國(guó)航空網(wǎng) m.k6050.com 航空翻譯 www.aviation.cn 本文鏈接地址：757 AMM 飛機(jī)維護(hù)手冊(cè) 儀表 CHAPTER 31 - INSTRUMENTS 1(42)
