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757 MAINTENANCE MANUAL
Monitor
 1)  The monitor assembly provides many of the monitor and miscellaneous system functions. These functions include computation and iteration monitoring, system clocks, real-time interrupts, transfer bus termination logic, and two non-volatile fault indicators (used to provide an indication of failures in the CAPS processor or power supply).
Pitch Servo
 1)  The servo assembly provides an interface between the CAPS processor and the elevator servo loop. Servo commands from the CAPS processor are converted to analog signals and then summed with the present servo position signal to provide the drive for the aircraft hydraulic servo valves.
Engage/Warn
 1)  The engage/warn assembly provides an interface between the CAPS processor and the autopilot servo engage solenoids. The assembly also provides discrete-to-TTL level translation of elevator, aileron, and rudder engage signals, and the left and right autopilot engage signals for use by the CAPS processor. Window comparators are provided to monitor the power supply voltages.
Cross Channel Receiver
 1)  The cross channel receiver assembly provides the FCC with an input buffer for data from the other two FCCs in the system. The input data is received on ARINC 429 buses and converted to parallel words for use by the CAPS processor. Separate input buffers are maintained for each of the other FCCs in the system.
Read/Write Memory
 1)  The read/write memory assembly provides 4k words of high speed CMOS RAM for use by the CAPS processor as scratch pad memory. The assembly also provides 32 words of non-volatile memory for storage of fault information. In addition to the memory circuits, transfer bus logic decoding for up to 13 outputs is divided. These outputs are used to enable devices which require no more than four transfer bus addresses.
Arm/Warn
 1)  The arm/warn assembly provides an interface between the CAPS processor and the autopilot servo arm solenoids. Circuitry is also provided for half of the warn output and for half of the dual FCC power supply monitor. Additional circuits allow the CAPS processor to examine the status of interface data for verification or safety reasons.
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757
MAINTENANCE MANUAL

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I/O Control

 1)  The I/O control assembly provides the processing control functions for the various I/O interface assemblies. The assembly services the I/O assemblies by any of three methods: unconditional periodic service, conditional periodic service, or interrupt service. The controller operates independent of the CAPS processor and communicates with the CAPS through I/O data path assembly or by means of an interrupt.

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I/O Data Path

 1)  The I/O data path assembly provides an interface between the I/O processor and the CAPS processor. The I/O data parameters are stored in the assembly buffer by the I/O processor. The buffer is also read/write accessed by the CAPS processor.

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CAPS Processor

 1)  The CAPS processor is comprised of a CPU control assembly and a CPU data path assembly. The CPU data path assembly provides the data manipulation and processing circuitry required to execute the CAPS instruction set. The CPU control assembly contains the circuitry required for operation and control of the processor system and program memory.

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Program Memory

 1)  The program memory assemblies contain the operating program (software) for the FCC. The software provides the commands which control the operation of the CAPS processor.

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Power Supply

 1)  GUN 051; the power supply assembly provides the required operating voltages for the FCC. The input to the power supply is provided by the aircraft 115V ac, 400 Hz system. The outputs of the power supply are 26V ac, +28, -28, +15, -15, +12, -12, +5 Vdc, and a 40 milliamp current source for an engage lever holding circuit contained in the mode control panel.
　
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