H19390 H19401
Yaw Damper Engage Interlocks 591
22-12-0 Figure 4 Feb 15/80
Page 8
BOEING PROPRIETARY - Copyright . - Unpublished Work - See title page for details.
591 Yaw Damper Test Circuit
Feb 15/80 Figure 5 22-12-0
Page 9
BOEING PROPRIETARY - Copyright . - Unpublished Work - See title page for details.
D. Typical BITE Control
(1)
The BITE provides a check of a majority of the signal computation circuitry. This is accomplished by comparing a programmed (predetermined and scaled) signal with a fixed reference signal. Tolerance and polarity of each signal is also checked.
(2)
The BITE controls are on the front panel of the yaw damper coupler. At the top center of the panel is the test number window which indicates the specific test being computed. Below, is a row of two colored indicators which illuminate to indicate the status of the particular test shown in the test window. The left indicator is green to indicate a PASS condition; the right indicator is red to indicate FAIL condition. Directly below the PASS light is the GO switch used to trigger the sequence of tests. Directly below the FAIL light is the LAMP TEST switch used to check the PASS-FAIL lamps as well as the seven-segment display indicators behind the test number window. At the bottom of the panel, directly below the test number window, is the BITE (OFF-ARM) switch. The ARM position supplies BITE voltages to the multiplexer (MUX), comparator, AUTOPILOT DISENGAGED lights, and card input stimuli, and prepares circuits within the unit for testing (initializes the unit).
E. Operation
(1)
Selecting BITE-ARM applies + 10 volts dc to the MUX, comparator, and card input stimuli circuits, 28 volts dc to the AUTOPILOT DISENGAGED lights, and 5 volts dc to the integrated circuits. With these voltages applied, a power reset and power reset removal initializes the unit during test 0. The power reset: resets the 14 stage counter to zero; time complete not logic starts the clock; the sequence counter is cleared to 0; the FAIL latch is reset to PASS; and a PASS signal is injected into the MUX channel and the comparator. The power reset removal: removes the reset from the 14 stage counter and starts a .64 second pulse; removes the clear from the sequence counter; and removes the reset from the FAIL latch. With time completed for test 0: the 14 stage counter stops and the injected comparator signal (PASS) causes the PASS output to the latch to illuminate the PASS indicators. This output is fed back to prevent a fail light at a later time. This terminates test
0.
(2)
To check the PASS-FAIL lamps and the seven-segment digital display, the LAMP TEST switch is pushed and held. Pressing the switch injects a fail signal into the MUX and comparator; the pass light feed back path is opened, allowing a comparator fail signal to trip the fail latch; the FAIL indicator illuminates; and 8 appears at the test number window as long as the switch remains pressed.
(3)
To select the next test, the GO switch is pressed and released. This action triggers a pulse which: resets the 14 stage counter and the FAIL latch; increments the sequence counter; and repeats power reset and power reset removal action as stated previously, except the sequence counter is not cleared and the memory outputs inject the proper stimuli for the particular test. When the GO switch is pressed after the last test, a dedicated memory output simulates a power reset back to test 0.
(4)
During normal testing procedures, the action of the GO switch, in conjunction with a flip-flop circuit, triggers a dual binary counter to provide consecutive test number data. This data is routed to the address inputs of two programmable read-only memories (PROM). The PROM outputs (binary form) representing the particular test number, is used to control a major portion of the BITE circuitry. The PROM outputs control test timing, provide tolerance and polarity information to the analog comparator, determines proper BITE stimuli for the cards being tested, pass appropriate read signal from the multiplexer to the comparator, and supply essential test number data to activate front panel seven-segment digital display. A 14 stage counter and two, four-bit comparators are combined to form a clock circuit. The output of these combined circuits is one of five available test times. The selected read outputs, tolerance and polarity signals are applied to the comparator to produce a single output. This output and the selected timing signal are applied to several logic gates to determine either a pass or fail logic signal: A pass signal activates the PASS indicator; a FAIL signal activates the FAIL indicators.
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